A context switch generally refers to the switching of the CPU (central processing unit) from one process or thread to another. A process or thread is, for example, an execution instance of a program or stream of instructions. A context describes an executing environment of a process or thread such as the virtual address space and state that is in the CPU's registers caches, including Translation Lookaside Buffers (TLBs), etc., program counter, and other execution state information, at any point in time. A context switch involves storing and restoring the state of a CPU such that multiple processes can share a single CPU resource. Modern processors may have multiple cores per CPU and multiple threads per core; for convenience in this patent application, CPU is used to refer to the hardware entities needed to execute a single instruction stream including cache, Translation Lookaside Buffer (TLB), registers, functional units etc. In a context switch, the state of the first process must be saved, so that when the CPU gets back to the execution of the first process, it can restore this state and continue. Generally, the state of the process includes all the registers that the process may be using such as the program counter and any other data that may be necessary.
Context switching generally involves suspending the progression of one process and storing the CPU's state for that process somewhere in memory, retrieving the context of the next process from memory and restoring it in the CPU's registers and returning to the location indicated by the program counter (i.e., returning to the line of code at which the process was interrupted) in order to resume the process.
Context switching requires considerable processor time, and incurs a substantial cost to the system, for instance, in terms of CPU time. Several primary factors contribute to the cost of a context switch: for one, registers and associated states must be saved when the process is switched out; for another, registers and associated states must be restored when the process is switched in; thirdly, registers and associated states associated with different caches such as the TLB, Segment Lookaside Buffer (SLB) and memory instruction and data cache is lost and must be re-created as misses occur. The costs incurred for first and second factors mentioned above are generally being offset by faster processors. The third factor, however, that involves the cache “footprint” which takes significant time to reload, has been greatly impacted by the widening speed gap between the processor and the memory. Further, because the misses to re-create the TLB; SLB, or instruction (I) and data (D) cache state stall the processor, it is particularly detrimental to processing performance. It is expected-that the performance impact on context switches, for instance, because of the process of reloading the cache “footprint”, will continue to increase and worsen as processor speed improvements out pace memory speed improvements.
Known techniques have focused on decreasing the amount of register states that need to be saved and restored across context switches. While such techniques help to reduce the cost of a context switch, it does not address the most expensive part of the context switch, that is, restoring the footprint. Accordingly, a method that would reduce the overhead impact in context switching of having to re-create different caches is desirable.